Now our partners and we need some positions for verification engineers and senior verification engineers. Description and requirements detail as below:

We're provides very good benefit programs and working conditions:

-       Attractive/Competitive 13-month salary + extra performance-based annual bonus program

-       15 annual leave days per year

-       Professional working environment

-       Flexible working hour

-       Personal Healthcare Insurance for employee and family

-       Personal Accident Insurance for employee and family

-       International Travel Insurance

-       Petrol and home ADSL Allowance

-       Daily lunch provided

-       Opportunities to travel and work overseas such as USA, Japan, India, China, Taiwan, etc.

-       And other benefit programs will be informed in the new hire orientation section

1. ASIC Transport Verification Engineer

Job Description

Perform ASIC verification testing for APM state-of-the-art Transport products.

Responsibilities

• Develop yourself to become expert in various Transport technologies and applications including OTN, SONET/SDH, Ethernet/Packet Optical Transport, Carrier Ethernet Switches at different data rates from under 10G, 10G, 40G, to 100G
• Develop your own expertise in object-oriented verification approach and advanced verification methodology AVM/OVM/UVM
• Develop test-benches and reference models for block-level and full-chip verification. This work involves working closely with APM global teams to create constrained random based test-bench and test cases, to ensure adequate feature and code coverage, and to help resolve test failures.
• Develop and implement OVM/UVM compatible VIP library for block-level and full-chip verification. Responsibilities will include developing protocol generators and monitors for various protocols/standards
  • OTN
  • SONET/SDH
  • Ethernet
  • GFP
  • Etc.
• Develop reusable verification environments to be used across multiple projects using System Verilog, System C and/or C/C++
• Verify the overall system architecture and all individual blocks, both analog and digital
• Work with both Analog and Digital Designers on system Model verification to ensure accuracy of the model
• Responsible for on-time delivery and quality of specification, verification of system model

Qualifications

• BS with 2-4 year or MS with 0-4 year of experience in Electrical Engineering/Computer Engineering or equivalent field with ASIC Verification focus
• Solid understanding of RTL Design (Verilog preferred)
• Strong knowledge of Perl, Python, TCL, UNIX shell, or equivalent scripting languages
• Knowledge of System Verilog, Matlab/Simulink and C/C++ is a plus

• Basic knowledge of any of the followings: TCP/IP, Ethernet over SONET/SDH (EoS), SONET/SDH, ATM, OTN, 8G/10G Fibre Channel, and/or MPLS protocols
• Good English communications skills, both verbal and writing

Additional desirable skills:

Any of the following is highly desirable but not required:

• Knowledge of test equipment such as OTU3 from JDSU, 10GE Ixia, JDSU TestPoint, Anritsu, ANT-20, OmniBer OTN, digital sampling oscilloscopes, logic analyzer is a plus
• Knowledge on Board Bring-up is plus

Location:

Center in Ho Chi Minh City, Vietnam.

2. Senior/Staff ASIC Transport Verification Engineer

Job Description

Perform ASIC verification testing for APM state-of-the-art Transport products.

Responsibilities

• Take a leading role in the development of system design for communication system transceivers
• Provide technical leadership and mentoring to the junior design/verification engineer
• Continuously improve your expertise in various Transport applications including OTN, SONET/SDH, Ethernet/Packet Optical Transport, Carrier Ethernet Switches at different data rates from under 10G, 10G, 40G, to 100G
• Continuously improve your expertise in object-oriented verification approach and advanced verification methodology AVM/OVM/UVM
• Develop test-benches and reference models for block-level and full-chip verification. This work involves working closely with APM global teams to create constrained random based test-bench and test cases, to ensure adequate feature and code coverage, and to help resolve test failures.
• Develop and implement OVM/UVM compatible VIP library for block-level and full-chip verification. Responsibilities will include developing protocol generators and monitors for various protocols/standards
  • OTN
  • SONET/SDH
  • Ethernet
  • GFP
  • Etc.
• Develop reusable verification environments to be used across multiple projects using System Verilog, System C and/or C/C++
• Verify the overall system architecture and all individual blocks, both analog and digital
• Work with both Analog and Digital Designers on system Model verification to ensure accuracy of the model
• Responsible for on-time delivery and quality of specification, verification of system model

Qualifications

• BS with 6~8 year or MS with 4~8 year of experience in Electrical Engineering/Computer Engineering or equivalent field with ASIC Verification focus
• Solid understanding of RTL Design (Verilog preferred)
• Knowledge of and experience in System Verilog, Matlab/Simulink and C/C++ is a must
• Strong knowledge of Perl, Python, TCL, UNIX shell, or equivalent scripting languages
• Some experience in any of the following: OTN, 8G/10G Fibre Channel, SONET/SDH, Ethernet over SONET/SDH (EoS), ATM, TCP/IP, and/or MPLS protocols
• Good English communications skills, both verbal and writing

Additional desirable skills:

Any of the following is highly desirable but not required:

• Knowledge of test equipment such as OTU3 from JDSU, 10GE Ixia, JDSU TestPoint, Anritsu, ANT-20, OmniBer OTN, digital sampling oscilloscopes, logic analyzer is a plus
• Knowledge on Board Bring-up is a plus

Location:

Center in Ho Chi Minh City, Vietnam.

Candidate interested in this position. Please send us your CV via: This e-mail address is being protected from spambots. You need JavaScript enabled to view it

HTGSOFT is constantly looking for talented more engineers, leaders, project managers for our projects, productions team in Vietnam and US. If you have the skill and the motivation to join us, please send us your CV via : This e-mail address is being protected from spambots. You need JavaScript enabled to view it